Selective transistor redundancy for combinational circuits to reduce faults

Now a days, CMOS devices are becoming more popular and with fabrication technology reaching nano levels, systems are getting additional vulnerable to producing defects with higher susceptibleness to soft errors. Soft errors are the errors that are caused by high density materials, coupling etc., the existing methods are not perfect in order to reduce the errors with increase in no of transistors. This paper is concentrated on coming with combinatory circuits for soft-error correction with less space overhead. This concept is predi¬cated on generating a random pattern series for testability of faults in a combinational circuit and protects the transistors, whose soft error detection high, this process is continued till the combinational circuit produces the correct output as similar as input. In this paper we are proposing a selective transistor redundancy algorithm which selects the transistor whose probability of failure is high and protects the transistor to reduce errors. This process is continued until a certain area overhead or threshold limit is obtained.