Device design of 3-nm node-complementary-field effect transistor (cfet)

With a common gate, this CFET vertically stacks n-type and p-type nanosheet MOSFETs. Here, the ideal CFET device dimensions are examined in order to improve the electrical properties and inverter performance. Performance is examined for a number of CFET vertical dimension factors, encompassing how many stacked channels there are, the vertical distance (Dnsh) between nanosheet channels, the distance (Dn/p) between MOS separations, and the channel thickness (Tnsh). The findings indicate that, in contrast to typical CMOS, CFETs may efficiently increase inverter performance without experiencing significant deterioration by reducing their Dnsh and Dn/p, even though doing so forces a harsh trade-off between various parameters due to other dimensional factors. Due to electrical coupling, the decrease in Dnsh and Dn/p in the case of electrical characteristics marginally but significantly raises Tmax and Rth. Thus, a key technique for the creation of sub-3-nm CFETs will be the lowering of Dnsh and Dn/p