Secure tap controller ip core

The objective of the work is to design and implement a reusable tap IP core in HDL. The standard IEEE 1149.1 popularly known as JTAG is an established technology and industry standard for on-chip boundary scan testing of SoCs. JTAG TAP controllers used as delivery and control mechanism for Design For Test also poses a security threat. The attackers may try to extract details or modify or controls the signals of internal logic using JTAG port as it does not preclude any protection measures. The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The paper also suggests the use of lightweight cryptographic ciphers to ensure the authenticity of devices in JTAG chain to defend against JTAG attacks. Also it may be used to ensure the communication secrecy between JTAG master and associated devices.