Implementation of i2c communication protocol with rtc and eeprom on FPGA

I2C bus defined by Philips providing a simple way to talk between IC’s by using a minimum number of pins. This bus is called the Inter IC or I2C bus. All I2C bus compatible devices incorporate an on- chip interface which allows them to communicate directly with each other via the I2C bus. This design concept solves the many interfacing problems encountered when designing digital control circuits. This paper implements I2C (Inter IC Communication) master bus controller for interfacing low speed peripheral devices using field programmable gate array. The I2C master bus controller interfaced with slave devices Real Time Clock (DS1307) and EEPROM. This module was designed using VHDL. The design was synthesized using Xilinx ISE Design Suite 14.7 and implemented on SPARTAN 3E XC3S200 FPGA.